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An associative memory architecture for modeling pairwise pixel interactions in imagery is proposed.
We have implemented a "hierarchical parallel solver" on a distributed memory architecture for this.
This paper presents a novel parallel memory architecture for multimedia computers.
The model can be used to optimize the on-chip memory architecture for a single dedicated software, multiple but replaceable applications, or coexisting applications in a multitasking environment.
As demonstrated on an industrial example, the application of the methodology results in a heavily power and/or area optimized custom memory architecture for a given application.
In this paper we present a low latency reconfigurable radiation tolerant memory architecture for mission-critical applications based on the RTSR (Radiation Tolerant Self-Repair) cell.
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The chapter also describes different memory architectures for MPSoCs.
This paper surveys the design of memory architectures for 3D CMPs.
Research on 3D stacking memory hierarchy explores the high performance and power/thermal efficient memory architectures for 3D CMPs.
We summarize current research into two categories: stacking cache-only architectures and stacking main memory architectures for 3D CMPs.
The latter was optimised and fully parallelised for shared memory architectures, for solutions on rectangular grids stretched in one or two directions.
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