Sentence examples for memory and array from inspiring English sources

Until now several architectures have been proposed like pipelined architecture, memory-based architecture, cache memory and array architecture.

A novel concept of dual control gate EEPROM (Electrically Erasable and Programmable Read-Only Memory) cell and array architecture are proposed.

We manipulated perceptual organization between memory and probe array; perceptual organization was either identical between memory and probe array (context+; Fig. 5a), absent since only the cued item was shown (context0; Fig. 5b) or disrupted since all non-cued items were changed between memory and probe array (context−; Fig. 5c).

Here, we manipulated perceptual organization between memory and probe array to control for this alternative explanation; perceptual organization was either identical between memory and probe array (context+; Fig. 5a), absent since only the cued item was shown (context0; Fig. 5b) or disrupted since all non-cued items were changed between memory and probe array (context−; Fig. 5c).

All non-cued items were not changed between memory and probe array.

Again, in this experiment, all non-cued items were rotated between memory and probe array to prevent grouping.

The interval between memory and probe array was 2000 ms for the iconic-cue and retro-cue conditions and 900 ms for the post-cue conditions.

We performed an additional experiment in which we manipulated perceptual organization between memory and probe array to test this alternative explanation.

To prevent that subjects used a strategy of grouping similar items together, we rotated all other items by 90 degrees between memory and probe array.

We presented only the retro-cue and post-cue conditions, and we varied the blank interval between memory and probe array between 1,000 and 5,500 ms for retro-cue conditions (Fig. 7c) and between 900 and 5,400 ms for post-cue conditions (Fig. 7d) in steps of 1,500 ms. All non-cued items were not changed between memory and probe array.

In this work, we exploit the global memory (accessible from all threads), the shared memory (accessible from threads of the same block), the local memory (registers and arrays, accessible from owner thread), and the constant memory (cached and not modifiable).