The maximum frequency obtained for this design is 83.1 MHz.
Moreover, the maximum frequency of operation of the design here proposed is smaller than those reported by competitors, which justifies the low levels of power consumption achieved of approximately 85 mW.
To obtain the best sensor parameters, we propose simple design procedure, which finds not only maximum frequency separation between two adjacent resonance frequencies but also lowest reflection coefficients at the resonance frequencies.
A maximum frequency of 10,000 Hz was chosen for the initial design because most of the frequencies to which the human ear is sensitive can be found below 10,000 Hz [15].
Figure 2 Simulated maximum frequency waveform.
Note that the maximum frequency shown in Table 3 is 154.5 MHz, but in our design, we have set this frequency to 100 MHz as explained previously.
The majority of variation in the five variables that measured frequency (start frequency, end frequency, maximum frequency, minimum frequency, and frequency at maximum amplitude; see Figure 1c) was explained by PC1 (Table S1).
The design is optimized with the help of device utilization summary, timing parameters, maximum frequency and memory support.
In this way, the reliable design makes the circuit lifetime five times longer, if we fix the maximum frequency ageing degradation at 2.0%.
We implement our design using Xilinx XC4VLX80 FPGA device which uses 24,263 slices and has a maximum frequency of 143 MHz.
