To evaluate the effect of inaccurate attenuation maps on hardware attenuation estimation employing xMLAA, typical MRAC-based errors were simulated, modifying the CT-based attenuation maps.
A key feature of the algorithm is that it supports easy mapping to hardware.
Thus, attenuation maps of flexible hardware components need to be scan-specific.
The algorithm has been mapped to hardware.
The work by Francillon et al. [17] maps the minimal collection of hardware and software components that are needed for a secure verification, based on a precise definition of the desired verification service.
Although, the framework is parametrical in respect to the mapping procedures for the fine and coarse-grain reconfigurable units, we provide specific mapping algorithms for these types of hardware.
Blob computing is a new approach that addresses this parallel computing challenge in a radically new and unconventional way: it decouples the mapping of computations onto the hardware from the software programming while still elegantly exploiting the space of the underlying hardware.
The mapping of the algorithm to hardware is described.
Hardware mapping of computations is done by a physical force-based approach that simulates forces between threads of computation (automata).
We believe that our technique provides several benefits such as improving parallelism of tasks and fast-and-valid mapping of software models to hardware architecture.
Due to the direct mapping of application tasks onto hardware resources, FPGA is able to complete one operation in a single clock cycle, which avoids the instruction fetching, decoding, and executing overheads as in the software processors.
