Because NW FETs function in accumulation and depletion modes, they allow lower operation voltage than thin-film FETs operating in inversion mode.
Consequently, this causes the substantial benefit for practical analog and digital applications especially for lower operation voltage, lower power consumption commercial and military products.
Compared with single-EML devices, double-EMLs devices showed higher EL efficiencies, higher brightness, and lower operation voltage attributed to wider recombination zone and better balance of carriers.
The downsizing of CMOS technology into the decananometer range has called for the redesign of the ESD protection devices because of the constraints of lower operation voltage and smaller breakdown voltage of the ultrathin gate oxide.
The programming and erasing speeds can be improved by BETL on both planar and NW channel devices, and the improvement is more obvious on NW channel devices with even a lower operation voltage.
The devices annealed at 500 °C have a lower operation voltage, lower barrier height, and higher non-linearity factor, which are beneficial for selector-less crossbar memory arrays.
Compared to other memory devices, the devices annealed at 500 °C have higher non-linearity factor, lower operation voltage, and lower barrier heights.
The RRAM devices annealed at 500 °C had a lower operation voltage, thinner WOx/W TE interface, lower barrier height, and stable data retention.
FeFET devices are also expected to exhibit a lower operation voltage, higher field effect mobility, higher transconductance, and higher ION/IOFF ratio than the other devices [20].
Comparing all devices, the devices annealing at 500 °C showed higher non-linearity factor with lower operation voltage, and stable data retention at a high read voltage of 0.5 V, which will have the potential for nanoscale non-volatile memory applications.
