Exact(12)
As presented in this paper, typical voltage swells during the recovery period have limited voltage unbalance, phase angle jump and discrete transients.
By studying the characteristics of the typical causes resulting in asymmetrical voltage swells, the PCC voltage during the fault recovery have limited voltage unbalance, phase angle jump and discrete transients.
The band limited voltage signal is then sampled at 32 kHz (sampling interval 31.25 μs > simulation time step 10 μs) and digitized with 12-bit ADC to make sure difference between peak dv/dt before and after the sampling remains less than 5%.
However, the site of synaptic activation often is distant from the recording site, and previous studies have demonstrated that somatic voltage clamp exerts limited voltage control across the dendritic arbor [10], [11], [12], [13], [14].
By independently adjusting the direct-current (dc) bias applied to the tuning comb electrode, the tuning capability was maximized under limited voltage source conditions.
The trap-unfilled SCLC is changed to a trap-filled SCLC at the trap-filled limited voltage (V TFL), thereby resulting in a further slope increase.
Similar(48)
The measured limiting voltage is 2.9 V with a voltage deviation of only ±0.065 V for the 12 measured dies.
Second, a second-order cone programming problem (SOCP) optimizer determines the maximum charge and discharge active powers for each ESS that maintains safe system operation limits (voltage limits, cables capacity, and reverse power flow limits).
When the upper limiting voltage was increased to 4.5 V, the crystal structure of P2-Na2/3[Ni1/3Mn2/3]O2 was irreversibly damaged due to over extraction of Na+ in 4.0 4.5 V.
The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion.
From the application point of view, avalanche hot-carriers appear to present new constraints, which may be managed through limiting voltage (to 1.5× 2× BVCEO), or through circuit designs robust to base current parameter shifts.
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