The architecture uses an efficient complex multiplier that has 25% less multiplications.
On the other hand, the Guo-Nilsson decoder needs less multiplications with some performance loss with 16-QAM.
This algorithm uses less multiplications with respect to the previous one and about the same number of additions, but at a price of a more complex architecture.
As we can see in Table 1, the low-complexity K-best T-LORD saves less multiplications and additions than those expected looking at the number of computed ED.
This algorithm uses less multiplications with respect to the previous one and about the same number of additions, but at a price of a more complex architecture. . the "rows-columns" method, that calculates a two-dimensional DCT (on a square block of pixels) as two one-dimensional DCTs.
Even though ideal initial conditions were used in all cases, the solution of the inhomogeneous BSE took less multiplications than the eigenvalue calculations in the region of the on-shell points of the ground state (corresponding to the first eigenvalue) and the first excitation (corresponding to the third eigenvalue), which are indicated by the vertical lines in the figure.
Our approach uses only a generic carry-less multiplication instruction, without any field-specific reduction logic, making the instruction applicable to multiple use cases, and therefore an appealing addition to the instruction set of a general purpose processor.
This research played a significant role in the process that eventually led to adding a carry-less multiplication instruction (called PCLMULQDQ) to the Intel Architecture.
The two latter concepts can be used for writing an efficient and lookup-table free software implementation of the Galois Counter Mode, for processors that have a carry-less multiplication instruction.
Our approach is based on three concepts: a) having a 64-bit carry-less multiplication instruction in the processor; b) a method for using this instruction to efficiently multiply binary polynomials of degree 127; c) a method for efficient reduction of a binary polynomial of degree 254, modulo the polynomial x128+x7+x2+x+1 (which defines the finite field of the Galois Counter Mode).
