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All simulations described in this paper were performed using a computer cluster composed of nodes with Intel R) Xeon(R) 2.66GHz processors (X5355, 4096 KB cache) and 8 GB (8048408 kB) of RAM memory.
For the small 1 KB cache, the access time is almost independent of the block size.
The cache conflict is high for the small configuration with 1 KB cache.
For instance with 64 KB cache size, the DAWP cache achieves 16.45% ~ 75.85% power gain for 2-way ~ 32-way structures, respectively.
For instance with 64 KB cache size, the DAWP cache achieves 4.91% ~ 26.96% latency gain for 2-way ~ 32-way structures, respectively.
The efficiency is increased with the increasing associativity, and the testing results with 64 KB cache show that the DAWP cache achieves 16.45% ~ 75.85% power gain and 4.91% ~ 26.96% latency gain for 2-way ~ 32-way structures, respectively.
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Between the 8 KB and 16 KB caches, the performance did not change, but energy consumption increased by 78%.
The PGA-I was executed on a multicore Intel Xeon E5504, with two CPUs, four cores each at 2 GHz, 256-KB cache L2, 4-MB cache L3, FSB at 1,333 MHz, 4 GB, Ubuntu 10.04 LTS (kernel 2.6.32).
The experiments are conducted using JM 18.0 reference software [13] and compiled with Microsoft Visual Studio 2010 using Intel i7 platform (Redmond, WA, USA) as described below: Intel Core™ i 7 CPU 930, running at 2.8GHz with four 32-KB D-Cache (L1), four 32-KB I-Cache (L1), four 256-KB cache (L2) with 8-way set associative, and 8-MB L3 cache with 16-way set associative and 8-GB RAM.
Nehalem Xeon 5000 series have such architecture features: (a) four cores integrated into one CPU, (b) hyper-threading technology supports 8 threads at most, (c) each core has a 64 KB L1 cache and 256 KB L2 cache, with an 8 MB L3 cache is shared by all cores and (d) Turbo Boost technology, dynamically adjusts the work frequent of cores.
The results are evaluated in Intel Core i7-5600U professor of 2.6 GHz with 128 KB L1 cache, 512 KB L2 cache, and 4MB L3 cache running on windows 10 operating system and on a Broadwell system.
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