Although the capacity of the first FeRAM had only a 256-bit density [111], with the incorporation of the modern semiconductor technology, ferroelectric nanostructures with much higher integration density have been integrated in a large scale [112, 113].
The three-dimensional integrated circuit (3D-IC), which enables better integration density, faster on-chip communications and heterogenous integration, etc., has become an active topic of research.
In order to implement better speed/power consumption and integration density (of course, for given cost) in integrated circuit (IC) chip, metal oxide semiconductor field effect transistor (MOSFET) has been scaled down with the help of various process/device solutions over the last a few decades; in fact, the Moore's Law [1] has been alive for long time.
Based on the current achievements on the controllable and selective growth of CNT arrays, as shown in Figure 19a, we suggest a new FeFET architecture by integrating CNT arrays with ferroelectric to further enhance the integration density of the memory devices.
Alternative architectures improving integration density and performances are analyzed.
The vertically aligned single MWCNT design can guarantee an ultra-high integration density, as well.
Low pressure helium mini-channel cooling is used to offer a high integration density.
The thermocouples are deposited by thin-film processes with high integration density on the wafer surface.
This process preserves the ultra-high integration density advantage unachievable on other flexible substrates.
System integration density increased tremendously in recent years, resulting in various problems for designers.
Moreover, forthcoming three-dimensional (3D) MPSoCs can achieve higher system integration density, but the aforementioned thermal problems are seriously aggravated.
