These processors differ from superscalar processors, which can issue multiple instructions per cycle from one instruction stream (thread); in contrast, a multicore processor can issue multiple instructions per cycle from multiple instruction streams.
This architecture allows threads to execute independent and divergent instruction streams, thus facilitating decision-based execution, which is not provided by the more common single instruction multiple data (SIMD).
In a processor, an instruction stream permeates a data stream.
The traditional memory hierarchy design can smooth the data stream and instruction stream.
The fill status of the prefetch queue depends on the history of the instruction stream.
Some microprocessors try to extract ILP from the instruction stream, that is, execute more than one instruction per clock cycle.
However, the bandwidth of the instruction stream and data stream are still the main challenge for high-performance microprocessor systems.
The eight SPs in the same streaming multiprocessor are connected to the same instruction unit, so they execute the same instruction stream on different data (called thread).
Dynamic superscalar processors contain logic that examines the incoming scalar instruction stream and groups independent scalar instructions into bundles of instructions that can be executed concurrently.
Several data streams can be permeated of the same instruction stream when the algorithm that is to be implemented allows it.
In the proposed mechanism, the instruction stream buffer stores the repeat block completely and suspends as far as possible the cache access to reduce access time.
