Instruction pipeline is extensively used in modern processors in order to achieve instruction level parallelism in pipelined processor architectures [1].
It consists of a 3-stage instruction pipeline, instruction decoding, a 16-bit ALU, four dedicated-use registers, and twelve working (or scratchpad) registers.
Thus, as a result of this, the performance of the processor increases because data accesses do not affect the instruction pipeline.
This allows instructions and data accesses to take place at the same time, and as a result of this the processor performance increases because data accesses do not affect the instruction pipeline.
Its core features are cache consciousness, vectorized execution, instruction pipelining and SIMD usage.
These include: multiple operations per cycle, hardware loop constructs, specialized addressing modes, and interlocked instruction pipelines.
In summary, the flexible 4-stage pipeline structure avoids the deep instruction pipelines of fetching, decoding, and registering read/write and ALU operations in conventional general purpose processors.
Modern processors have multi-stage instruction pipelines.
The inner loop was completely unrolled to reduce the loop overhead, the dependency graph was created and the instructions were pipelined to reduce the number of cycles.
In VLIW processors, instructions are pipelined with an out-of-order execution, thus, iterations are initiated in parallel at a constant rate called the initiation interval (II) [19] (Fig. 6).
A branch instruction might render preloaded instructions in the pipeline useless if they entered it before the branch jumped to a new part of the program.
