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We have developed an efficient implementation to compute the 2D fast Fourier transform (FFT) on a new very long instruction word programmable mediaprocessor.
Complex instructions can be built from the Diamond 545CK DSP's operation primitives by bundling three operations into a wide instruction word.
Digital signal processors (DSP) based on very large instruction word (VLIW) architectures are potentially well suited for software-based implementation of video codecs.
The most efficient architecture for sequential problems is a two-level pipelined VLIW (very long instruction word) architecture with few parallel functional units.
Very long instruction word (VLIW) architecture is widely used in the design of digital signal processors (DSPs) and application-specific processors because of its hardware simplicity and high efficiency.
A standard solution for a multimedia coprocessor resembles of single-instruction multiple-data (SIMD) engines into architectures exploiting ILP at compile time, such as very long instruction word (VLIW) and transport triggered architecture (TTA).
Similar(25)
This paper presents an instruction scheduling and cluster assignment approach for clustered very long instruction words (VLIW) processors.
This paper presents a fast context-based adaptive variable-length decoding (CAVLD) method of H.264/AVC with a very long instruction word-based bitstream processing unit (BsPU) designed for entropy decoding of multiple video formats.
The DPU in the Storm-1 processor includes an instruction memory of 2,048 384-bit instruction words.
An instruction defines what data transports are to be performed on each bus, which leads to wide instruction words.
In Fig. 3, FU is Function Unit, RF is Register Files, VLIW is Very Long Instruction Words, and CGRA is Coarse Grained Reconfigurable Array.
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