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In a processor, an instruction stream permeates a data stream.
The fill status of the prefetch queue depends on the history of the instruction stream.
The traditional memory hierarchy design can smooth the data stream and instruction stream.
Some microprocessors try to extract ILP from the instruction stream, that is, execute more than one instruction per clock cycle.
However, the bandwidth of the instruction stream and data stream are still the main challenge for high-performance microprocessor systems.
The eight SPs in the same streaming multiprocessor are connected to the same instruction unit, so they execute the same instruction stream on different data (called thread).
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This architecture allows threads to execute independent and divergent instruction streams, thus facilitating decision-based execution, which is not provided by the more common single instruction multiple data (SIMD).
Then, the controller will interpret the instructions in the execution command stream buffer.
Each streaming multiprocessor has one instruction unit, eight stream processors (SPs), and one local memory (16 KB), so it has 16 SPs in total.
SIMD is a single instruction multiple data stream, capable of copying multiple operands and packing them into a set of instruction sets in a large register.
The Complex Streamed Instruction (CSI) set is an instruction set extension targeted at multimedia applications.
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Justyna Jupowicz-Kozak
CEO of Professional Science Editing for Scientists @ prosciediting.com