The one-level memory system architecture of the processor includes 16-KB instruction and data caches and 16-KB instruction and data on-chip RAM.
However, the instruction and data buses share the same memory space.
Microprocessor performance is degraded by bus contention between instruction and data memory traffic.
The simulated memory system included a direct-mapped mixed instruction and data cache.
Instruction and data is stored in a piece of M9K block memory.
Custom arrangements of instruction and data cache are presented to optimise off-chip memory consumption and improve system performance.
This execution model supports specification of the microarchitecture including pipelines, control, and the memory hierarchy including instruction and data caches, the assembly language syntax, and the binary representation.
A number of potential predictors of performance were investigated, including: demographic data, type of interface, type of instruction, and data from two cognitive style tests.
These examples are essentially focused on instruction recovery but the algorithms also work on data recovery or on a combination of both instruction and data recovery.
The idealized single-chip NP architecture used essentially contains a number of identical multithreaded general-purpose processors, each having its own instruction and data caches.
At the architecture level, fine-grained data transport in TTA datapath and multi-threading method are adopted to exploit instruction and data level parallelism respectively in the graphics applications.
