Sentence examples for increase erroneous from inspiring English sources

Similarly, later elaboration on the conceptual or perceptual properties of misleading information about a previously seen video can increase erroneous reports that this information had actually been viewed, in contrast to a control condition involving non-elaborative verbal manipulations (Zaragoza, Mitchell, Payment, & Drivdahl, 2011).

He warned that adding a citizenship question would be "very costly" and would "harm the quality of the census count by increasing erroneous enumerations".

Lower thresholds are suitable when low rejection rate (high sensitivity) is required at the expense of increased erroneous verifications.

Interestingly, neither the ITT nor the PP approach can be recommended under simulated scenarios, adding to the literature that both approaches could provide increased erroneous results.

Increasing allowed alignment mismatches helps overcome missing genotypes, inaccuracies in the reference genome, and errors in the sequence reads, but also results in increased erroneous sequence alignment, particularly when aligning shorter reads.

Roll axis precision is about a factor of 10 worse [57], however misalignment here only leads to an increase in erroneous detections (e_{d}) on the CubeSat.

However, the asynchronies between the hands did not increase in erroneous trials.

Most haloarchaeal genomes have a higher proportion guanine and cytosine bases that cause an increase in erroneous identification of start and stop codons for most gene calling algorithms (Aivaliotis et al. 2007).

Another important stat is that Facebook's monthly active and daily active users in the US and Canada increased, despite erroneous recent claims from third-party data providers and critics that Facebook had lost users in US.

Although the erroneous increase in IL-17 levels may have been due to the heterophilic binding by serum RF [ 51, 52], there were no significant differences in RF positivity or titers between responders and non-responders in the present study.

Our most significant finding from this study is that the devices in on-chip memory cells cannot be scaled at the same rate as devices in logic circuits due to the increasing number of erroneous memory cells with voltage scaling, requiring strong fault-tolerance techniques.