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Many repeating and similar instructions are frequently transferred in NoC.
However, shared resources in NoC architectures can result in unwanted variation in spike packet transfer latency.
Nevertheless, the buffers also constitute the major leakage power consumers in NoC implementations.
Evaluation results show considerable reduction in NoC power consumption and packet latency.
Communication among the IPs in NoC can be customized by users through the lottery router.
An important research in NoC design is the tradeoff between area/power and performance.
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In this chapter, we present an NoC design that takes into account a well-known parallel programming model, message passing interface (MPI), to boost applications by exploiting all hardware features available in NoC-based multicore architectures.
Since the number of possible scenarios in NoC-based multi-cores is typically prohibitively high [17], a number of research activities aims at developing design-time (off-line) heuristics to reduce the number of operating points in the design space exploration (DSE) process [17].
This efficiency makes the proposed method a powerful asset for reliable routing in NoCs.
We propose three dynamic frequency tuning techniques, FreqBoost, FreqThrtl and FreqTune, targeted at congestion and power management in NoCs.
In this work, we present a mechanism for a global and dynamic admission control in NoCs dedicated to real-time systems.
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