Sentence examples for implementation faults from inspiring English sources

In the mutation criterion typical implementation faults are used to generate testing requirements.

In the proposed methodology, selection of fault models and implementation of fault injection and evaluation processes is addressed.

In the current implementation, the faults that need repaired are generic and represent bugs, vulnerabilities, exploits, or any other undesirable behavior, but the faults do not spread as computer worms do.

However, a higher vertical and horizontal resolution than that used for this study and the implementation of faults into the model would be needed, which in turn would require an improved structural and (hydro geological database.

The focus here is on fault detection and isolation (FDI) and the implementation of fault-tolerant strategies within the control algorithm.

To analyze human error in human computation systems, we join together human error concepts from Human Error Theory [23] and concepts related to the implementation of fault prevention and tolerance in computing system from Human-in-the-Loop [25] and machine-based distributed systems [43] literatures.

This paper discusses the design and implementation of fault aware collective algorithms for tree structured communication patterns.

The experimental results validate that the SDMP is more effective than the other three manifold learning methods for implementation bearing fault diagnosis, and it is more robust when deal with noise interference signal.

The main feature of this architecture is the possibility of deployment in a distributed multi-platform system and implementation of fault isolation by running the CF stage in a separate low-throughput reliable machine for stand-alone degraded mode operation.

The focus is on the implementation of fault tolerance, autonomous operation and operational flexibility by means of specific linked data structures and code execution mechanisms that can be interpreted as a kind of object oriented model for mission sequencing.

Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs.