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The suggested unit serves as universal basis for high-level image processing implemented on programmable chips, which enables a new generation of integrated high performance embedded vision systems maintaining reasonable system costs due to design reuse of basic units.
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This paper describes a study of parallel image processing algorithms implemented on a one-dimensional DSP array.
We have tested the scheduling technique on several image processing applications implemented onto a heterogeneous target architecture composed of two processors coupled with a configurable logic unit (FPGA).
To do this, an experimental study using the high speed visualizing and image processing was implemented to investigate the separation trajectories of bubbles under various bubble sizes and Reynolds numbers.
In the literature, we can find several GPU versus FPGA comparative works, for instance, in [3] five relatively simple image processing algorithms implemented on a Xilinx Virtex 4 FPGA and a GeForce GTX 7900 GPU are examined.
Image processing was implemented in c++ using ITK libraries for image manipulation [ 30].
The proposed automated image processing chain is implemented both on a general purpose processor and using the developed hardware architectures as co-processors in a FPGA based system.
Image processing algorithms were implemented using the MATLAB Image Processing Toolbox (MathWorks, Cambridge, UK) and C++.
Some image processing algorithms were implemented with the help of Open Source Computer Vision Library [ 15], and the graphical user interface was designed using Nokia Qt (a cross platform application and UI framework).
The domain of interest for this paper is using both neuro-fuzzy network and simple image processing techniques to implement traffic flow monitoring and analysis.
The main core of the image processing unit has been implemented by the differential algorithm procedure.
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