This high memory access ratio of the MC module demands for highly optimized memory accesses to improve the total performance of the decoder.
The HP Proliant SL390 architecture provides a high-bandwidth memory access, through the Intel QPI Speed 64GT/s; therefore, the global performance improvement is less significant than in the Q6600 platform.
The results show good efficiency in terms of the utilisation of hardware despite the high-latency memory accesses and good scalability across relatively large clusters of cores.
Moreover, to improve the overall performance, memory accesses should be coalesced, which means a higher memory throughput can be achieved when memory access is consecutive and bank conflicts during shared memory access are avoided.
At the moment, the DDR3 memories are preferred for such implementations thanks to their fast memory access, high bandwidth, relatively large storage capability, and affordable price.
Thus, CASE 1 implies higher arithmetic computations, however less memory access, than CASE 2. The final objective of this work is to illustrate for which system configuration it is more interesting to use TBICM-ID-SSD TBICM-ID-SSD TBICM-ID-SSD
If the processor is carrying out certain computations (utilissation of more than 1 %), then we adopt a probabilistic approach in modelling γ, such that the more total memory is in use, the higher in probability that a memory access is performed: γ = memoryUsage ∑ i = 1 n s i, (19) .
This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel.
Global memory in recent GPUs is at least 1 GB which restricts the number of states in the observation and estimation, but both memory access is high enough for our computations.
The better performance however also brings higher requirements for computational complexity and memory access.
