Exact(4)
This chapter presents an overview of electronic equalization and adaptation techniques with reference to their high-speed implementation.
The proposed circuit is a compact, high-speed implementation of the chaotic map based on the hyperbolic tangent function.
This high-speed implementation is achieved at the expense of adders.
By decomposing the channel matrix of an M-stream MIMO system into a generalized elementary matrix structure, the detection problem becomes a generalization of that of a two-stream detection problem, which admits a simple architecture suitable for high-speed implementation.
Similar(56)
This work proposes two optimization techniques for high-speed implementations of the required multiplications with the least possible number of FPGA components.
The data path word length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area.
We have developed a high speed implementation of the pseudo-random single photon counting method which was proposed in our previous work.
Recently, an ultra-high-speed implementation of this technique in an experimental application in ophthalmology showed elimination of motion artifacts and the need to re-align A-lines, thus enabling rapid and accurate 3D mapping of the retina and the optic nerve [ 24].
Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations.
Drawing upon this knowledge, a high-speed parallel implementation has potential for performing inference of many simultaneous concepts in real-time, realizing cognition as it perceives the current state of its environment.
In this work, an efficient and high-speed VLSI implementation of the bit-serial, digit-serial and bit-parallel optimal normal basis multipliers with parallel-input serial-output (PISO) and parallel-input parallel-output (PIPO) structures are presented.
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