We evaluate our implementation in a testbed of BSD routers over a FastEthernet network, and we sketch how the QoSbox can be implemented in high speed architectures.
This middleware offers better end-to-end bandwidth performance than the traditional TCP-based alternatives, while it hides the heterogeneity of the underlying high-speed architecture.
In this paper, we address this problem and develop a memory-efficient high-speed architecture for multi-level two-dimensional DWT.
We investigate high-speed architectures for the binary tree traversal and show that the traversal approaches discussed can be extended to m-ary tree of height h.
Xiong et al.[13] proposed two line-based high-speed architectures by employing parallel and pipelining techniques, which can perform j-level decomposition for N × N image in approximate 2(1 - 4-j)N2/3 4-j N2/3 4-j)N2/3 4-j N2/3cles.
This paper presents a novel digital sinusoidal pulse-width modulation (SPWM) technique based on immediate calculation of duty cycle count (DCC) values of pulses with high speed Harvard architecture based RISC controllers.
This paper presents the design of high speed parallel architectures for convolutional encoders and its implementation on FPGA devices.
We also present a high speed hardware C2BF architecture with off-chip memory and fast cache replacement method.
They present an field-programmable gate array (FPGA) implementation of a high speed MAP decoder architecture for turbo decoding achieving 346 Mbps.
The paper presents high speed and computationally efficient architecture for the recursive interpolation filters for digital audio applications.
This paper presents a novel, modular, high speed, original FPGA hardware architecture implementation for HSI2RGB conversion in addition to a novel, multiplierless, log-based, modular RGB2HSI colour space converter architecture and its improved, faster, pipelined version.
