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This paper presents an area-efficient twos complement high radix division algorithm and its architecture.
The advantage of using high radix division is to generate more quotient bits per iteration while binary division results in one bit per iteration.
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This paper presents a novel area-efficient two's complement high radix divider without affecting the high speed of the radix-2k structure.
A high radix Montgomery multiplication algorithm without final subtraction is used to perform this operation.
Reducing the load capacitance C or the switching frequency 'f' Pipelining Memory partitioning and reducing the twiddle ROM size Using higher radix, mixed radix algorithms, and radix factorization Using energy-efficient processing blocks.
This converter is derived through the use of higher Radix Montgomery's modulo multiplication for simplifying the hardware.
The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has been refined in terms of throughput and latency with the introduction of redundant arithmetic and higher radix techniques.
To achieve this, we introduce group majority signals similar to group propagate and generate signals in parallel prefix computations, use them to reformulate the carry expressions of a previous radix-4 FA, and as such we could extend it to higher radix FAs.
Using higher radix, mixed radix algorithms, and radix factorization.
Hardware solutions for FFT usually implement higher radix algorithms like radix-4 and radix-8 due to the reduced number of computations but at the cost of increased complexity of the algorithm.
For lower computation cycle counts, Higher radix algorithm should be used.
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