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My initial research at NEC Labs addressed hardware verification — ensuring that complex hardware systems worked correctly.
In the past my group has worked on fundamental problems in hardware verification.
This chapter illustrates the concepts of hardware verification environment and co-verification.
The hardware verification environment and test benches are closely related to co-verification.
Among the many areas of application are hardware verification, model checking, and symbolic graph algorithms.
This chapter discusses the relationship between co-verification and the hardware verification environment.
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In order to verify the proposed topology, MATLAB – simulations and hardware verifications are carried out and results are presented.
Moreover, the use of the Leon2ViP virtual platform, with fault injection capabilities, allows an early software-before-hardware verification and validation and also a hardware software co-simulation.
For example, in chip design, a lot of the issues that have to do with hardware design verification are of this sort.
A new languages were recently introduced to the hardware design verification environments to express constraints that the design must conform.
One of the causes is software engineers cannot easily modify the simulation environment without some help from hardware or verification engineers.
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