Comparing the overall software and hardware execution times, hardware acceleration provides a speed-up of 1,300 ×.
To summarize, both cases differ in space (of the hardware design) and (execution) time in terms of clock cycles.
In this paper, this relation is further explored, for the design of feasible IBWR scheduling algorithms, in terms of hardware implementation and execution time.
The software realization does not need to introduce needless synchronization, and hardware implementations can use different schedulers for the refined clocks to control the trade-off between resources (space of the hardware design) and execution time.
An efficient implementation should efficiently implement all these steps from the perspective of execution time, hardware resources, and robust performance.
This paper models hardware/software partitioning as an optimization problem with objective of minimizing power consumption under the constraints: hardware area A and execution time E.
In order to accelerate the algorithm, one can proceed with the parallelization of the algorithm and/or map it directly onto hardware to achieve faster execution time.
From Equation 3 in Section 3 (assuming we ignore processor temperature), it is only related to λ (hardware constant) and T (execution time), i.e. E static =λ×T.
The optimization is driven by the minimization of required hardware area, the imposed execution time and the necessary power consumption of the final implementation, and yet avoiding hot spots.
Hardware-dependent profiling exposes the execution time and memory cost under conditions of using specific hardware.
For large sequences running on our particular hardware, the GPU implementation reduces execution time by a factor of close to 60 compared with an optimized serial implementation, and by a factor of 116 compared with the original code.
