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Here, we face the challenge to combine flexibility with parallel scalability and hardware efficiency.
This paper presents a new ternary operator for cyclic redundancy check in ternary logic with high hardware efficiency.
The guiding principle in designing HIDE was the satisfaction of the dual requirement of abstract hardware design and hardware efficiency.
In comparison with other recent block ciphers, the implementation results of ICEBERG show a significant improvement of hardware efficiency.
Such a (4096, 2048) LDPC code has been adopted in a data transmission system due to its excellent error performance and hardware efficiency.
A complete design space exploration for the decoder architectures in terms of decoding performance and hardware efficiency is discussed in later sections of this chapter.
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Compared to the traditional ways, this methodology enables us to construct both decoding-performance-aware and hardware-efficiency-aware LDPC codes in a short time.
Finally, we propose a feasible micro-architecture of multi-core processor for C-RAN, called as CRANarch, the performance results show its improved hardware utilization efficiency and power efficiency when used in C-RAN data centers.
The radiative transfer model is very suitable for the GPU implementation to take advantage of the hardware's efficiency and parallelism where radiances of many channels can be calculated in parallel in GPUs.
By using the characteristics of the CSD structure, the circuit was able to be simplified and also the calculation speed was raised to increase the hardware's efficiency.
To minimize the critical path to one multiplier delay and to achieve 100% hardware utilization efficiency, the serial operation is optimized using parallel computation in advance with pipeline operation of independent path.
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