Sentence examples for hardening technique from inspiring English sources

This paper proposes a new circuit level hardening technique for reduction of soft error failure rate in DG-FinFET (double gate FinFET) based static random access memory (SRAM).

A deep UV hardening technique was applied, respectively, before the ion milling shaping of graphene channels and before the deposition of Cr/Au layers for the lift-off fabrication of FET electrodes to ensure the removability of the photoresist.

We then evaluated our program hardening techniques on this framework.

While there are many surface hardening techniques in use they have their own limitations.

Majority voters are typically used in redundancy hardening techniques aiming to increase the reliability of nanoscale circuits.

Impact fatigue characteristics may be enhanced by surface hardening techniques such as carburizing, nitriding and steel shot bombardment.

Hence, this work first analyzes Single Event crosstalk on recent technologies and then proposes hardening techniques to reduce Single Event crosstalk.

Hardening techniques for CMOS combinational logic have been developed to address the problems associated with Single Event transients, but in these designs, Single Event crosstalk effects have been ignored.

Among the surface hardening techniques, ion nitriding has proven to be a good candidate for treating powder metallurgy tool steels, since the parts are less susceptible to distortions, as can occur on other conventional surface treatments.

Since the cornerstone of their logic and interconnect resources is the multiplexer, this work introduces a defect-tolerant multiplexer, more resilient to single transistor defects (stuck-open, stuck-closed and gate shorts) than other multiplexer architectures studied in the paper, and more area-efficient than other existent hardening techniques.

Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports.