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Recently, 3D NoC has become more important than 2D NoC due its new geometrical arrangement and also reduces the wire length from global interconnect to local interconnect.
There are many approaches for addressing the global interconnect issues including reverse scaling, LC transmission lines, 3D integration, optical interconnects and carbon nanotubes.
We also present the design of two symmetric low-swing driver receiver pairs for driving signals on the global interconnect lines.
However, exponential increase in driver resistance in subthreshold region and increased global interconnect capacitance will become a major hurdle in improving the speed of subthreshold interconnects.
In recent years, since the inception of Through-Silicon-Vias (TSVs) to realize vertical channel, 3D stacked NoC architecture attracts a lot of interest as it offers improved performance and shorter global interconnect.
It has been found that aspect ratio scaling significantly reduces the interconnect delay and switching energy and at minimum aspect ratio, Cu wire performs better than even an optimized mixed CNT bundle for global interconnect length under subthreshold conditions.
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Manipatruni, S., Lipson, M. & Young, I. A. Device scaling considerations for nanophotonic CMOS global interconnects.
It is shown that the optimized low swing CMDR technique is efficient for global interconnects of the length equal or longer than 5 mm, and the improved buffer insertion technique, NEBI, is a perfect choice for the short global interconnects.
It also proposed device and interconnect optimization techniques to achieve higher performance and to reduce crosstalk in future subthreshold global interconnects.
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