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The common emitter current gain, gate sweep characteristics and sub-threshold sweep characteristics are measured after each exposure.
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Fig. 2 a I-V characteristic without annealing as no gate swept.
A key feature of these devices is the presence of large hysteresis in their transfer characteristics (IDSVGS curves) between forward and reverse gate sweeps.
Figure 2a, b show the drain current-voltage curves of the inverted FET without annealing and just after annealing as no gate swept, at a small drain-to-source voltage (V ds ) of 50 mV, respectively.
c Output characteristic for back-gate swept from −40 to 40 V just after annealing.
b I-V characteristic just after annealing as no-gate swept.
By using the maximum slope of the I ds -V g plots, at V ds = 0.05 V, a field mobility for back-gate sweeps and top-gate sweeps are, respectively, 50 cm2v-1s-1 and 75 cm2v-1s-1 in our measurement range.
Arrows indicate gate voltage sweep directions.
Therefore, the FETs show n-type characteristics in relatively small gate voltage sweep range.
A gate voltage sweep has been applied to the nanowire transistor by keeping a fixed Vsd = 0.025 V value.
A gate voltage sweep from inversion to accumulation and from accumulation to inversion is shown on the figure by arrows.
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