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It specifically concentrates on floating gate devices, which dominate today's products.
High power is not necessary for operation of these logic gate devices.
For bottom gate devices we identify the surface energy of the gate dielectric to predominantly dictate the device mobility.
The n- and p-type thin film transistors (TFTs), inverters, and NAND gate devices were fabricated using photolithography-based techniques.
Partial electron-yield NEXAFS is sensitive only to the surface of the film, and thus it is most relevant to the channel of the top gate devices.
However, practical realization of multiple gate devices face with technological issues, mainly linked to the use of very thin films or very narrow active areas.
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The deep trapping gate device concept for charged particle detection was recently introduced in Saclay/IRFU.
Finally, several real resistive gate device failure cases were examined using these same methods.
Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a mid-gap metal gate device with low doped Si layer have been analysed.
For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node.
As device scaling is entering the sub-25nm range, multiple gate device architectures are needed to fulfill the ITRS requirements, since they offer a greatly improved electrostatic control of the channel.
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