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"Method and apparatus for power reduction during lane divergence". U.S. Patent Application 13/605,460, filed September 6 , 2012
Dynamic Voltage Frequency Scaling (DVFS) is a widely used technique that running applications at reduced CPU frequency/voltage trades increased execution time for power reduction.
Experimental studies have proved that the hardware innovations for power reduction are fully exploited only with the proper design of upper layer software.
Increasing demand for power reduction in computer systems has led to new trends in computations and computer design including reversible computing.
The suits, filed in South Korea, Japan and Germany, involved 10 claims of infringements mainly involving patents for power reduction during data transmission, 3G technology for reducing errors during data transmission and wireless data communication technology.
This paper presents SRAM energy analysis utilizing multi-threshold (multi-Vth) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device combinations for energy efficiency improvement.
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Owing to maximum transmit power threshold, the value of power reduction for upstream SU v i is equal to ( {overline{p}}_i-{p}_i(t) ).
As shown in Figure 14, the effectiveness of power reduction for DVB-S2 at various data rates is very good, even at high SNR values.
Variable threshold voltage schemes have become popular for standby power reduction.
This chapter discusses the main techniques proposed in the literature for dynamic power reduction in field programmable gate arrays (FPGAs).
Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique.
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