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One remaining issue is the evaluation of the threshold for latch-up caused by MeV-level particles and to embed a latch-up protection circuit in the chip.
Then my tray wouldn't latch up.
Pull the latch up and away from the clasp.
Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks.
Different case studies are presented for ESD protection based on latch-up immune SCR devices.
During latch-up tests, hundreds of milliamps of current are sunk by every pin of the device.
The optimized ZTLDMOS-SCR devices are very attractive for constructing effective and latch-up immune high voltage ESD protection solutions in power integrated circuits.
In our testing, the receiver of the OLT transceiver and 12-channel receiver was tested for SEU only, and no latch-up and interrupt were observed during the exposure.
No single event latch-up was detected for the CMOS ASICs up to a proton fluence of 2×1012 cm−2×1012
Measurements and mixed-mode simulations are used for the analysis of transient-induced latch-up (TLU) in CMOS IC.
Furthermore, the classical guard ring latch-up protection approach fails for a transient trigger.
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