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This allowed facing up directly to the time leak point, where better performance improvement could be achieved to replace source code functions for custom instructions.
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In this paper, we present a technique for custom instruction (CI) extension considering process variations.
The Nios II processor supports different types of custom instructions.
It can be used as a subroutine by a larger procedure that solves the custom instruction selection problem by enumerating different subsets of custom instructions to synthesize.
With the use of custom instructions, an improvement was reached of 23%, on average, but close to a 55% improvement, in the best case, which supposes a great amount of savings in time spent for execution.
However, existing instruction set customization methodologies do not lend well for mapping custom instructions on to commercial FPGA architectures.
The two major new components are responsible for fine-grained application code profiling and identification of custom instruction candidates.
A novel clustering strategy is used to estimate the utilization of the LUT (Look-Up Table) based FPGAs for the chosen custom instructions.
In this paper, we propose a heuristic to identify profitable custom instructions for designs with arbitrary area constraints.
The chapter states that in this manner, the search space for the custom instruction selection problem can be explored.
In this paper, we propose a design exploration framework that provides for rapid identification of a reduced set of profitable custom instructions and their area costs on commercial architectures without the need for time consuming hardware synthesis process.
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