Sentence examples for fault simulation time from inspiring English sources

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches.

From Figures 13 and 14, packet delivery ratio and throughput decreases while increasing simulation time for fault-tolerant DSR.

By this reduction of simulation time candidate faults could be detected that would have been impossible otherwise because of excessive CPU time [7].

The simulation conditions are as follows: the transmission line experience an A-G fault at 0.1 s; the fault is cleared at 0.155 s; total simulation time is 0.5 s.

All simulations were performed in PSCAD/EMTDC with a simulation time step of 10 μs and the fault was applied when t = 2.5 s in each simulation case.

Fault location: 50% of line 2. For reduction of the simulation time, the dead time for the second reclosing is changed to 4 s instead of 15 s.

Packet delivery ratio decreases up to 30% for fault-tolerant DSR, whereas fuzzy trust DSR maintains 60% packet delivery ratio for simulation time = 500 ms.

The simulation time step is set to 13.88 μs to see the impact of fault propagation.

Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.

It can be known from Fig. 9 that after the fault is cleared the electrical center lies in circuit branch L19-30 and L33-34 and does not migrate in the simulation time.

The chapter then discusses fault simulation.