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The fault injection is composed of injecting SEUs into user design memory, and used configuration memory of the exploited FPGA.
Another technique is fault injection.
A fault injection flow based on pipeline is proposed to speed up the fault injection.
The fault injection test bench procedure requires automated fault injection, programmable fault load conditions and combined analogue/digital domain verification.
In order to speed up the fault injection flow, this paper improves the fault injection from three key points.
Cenzic, also based in Silicon Valley, has devised a novel approach to security testing called "fault injection".
The proposed fault injection platform can repair the accumulated SEUs automatically by itself after completing an injection flow which can ensure that the next fault injection is valid.
This paper presents a technique for rapid transient fault injection, regarding the CPU time, to perform simulation-based fault-injection in complex System-on-Chip Systems (SoCs).
Simulation-based fault injection provides a high observability adequate for error propagation analysis.
Measurements of system overhead, failover performance, and preliminary validation using fault injection are presented.
Previous techniques for SER estimation are mainly based on fault injection and random simulations.
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