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Fig. 1 Schematic diagram of the three fabrication procedures for the ordered VFS PZT NC arrays.
We detail the fabrication procedures for the polymeric systems and their utility in various experimental models.
Herein, the typical fabrication procedures for carbon nanostructures using interfacial engineering such as emulsion, dispersion, and vapor deposition are summarized.
The overall fabrication procedures for the Fe3O4@SiO2-MPS-AM-DMC-AMPS core-shell nanoparticles are schematically illustrated in Scheme 1a.
Possible scenarios for device structure and fabrication procedures for the ultimate nano-CMOS technology at the end of Moore's law will be highlighted.
Also, fabrication procedures for the TBM box assembly are presently under development for the establishment of an optimized assembly sequence/scenario and development of standardized welding procedure specifications.
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Figure 1 Fabrication procedure for ordered arrays of ZnO nanolines with improved electrical conductivity.
In addition, easy fabrication procedure for the high frequency 2-2 piezo-composite arrays was proposed.
(a) Fabrication procedure for forming Si nanostructures using spin-coated Ag ink nanoparticles and subsequent ICP etching.
Our proposed fabrication procedure for making devices having the gate-all-around cylindrical (GAAC) device architecture is also discussed.
(PDF 149 KB) 11671_2011_430_MOESM2_ESM.PDF Additional file 2 Schematic of the lithographic fabrication procedure for the SiO 2 line arrays used as structured substrate for the self-assembled AgNPs.
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