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Subsequently, dry etching was performed using inductively coupled plasma to etch down to the buffer layer to form the GaAs fin and simultaneously offer better device isolation.
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The glass is then etched down to the inner layer, leaving the design outline in relief.
Silicon substrate beneath the GaN grating region is patterned from backside and etched down to the AlN layer by DRIE, where the AlN layer serves as a definite etch stop (step e).
In order to obtain the symmetrically formed vertical comb structure with high aspect ratio, the double-SOI wafer was etched down to 300 μ m as far as by using KOH solution and the buried oxide was used as an etch stop layer.
The cantilever tip (NCLAuD, Nanosensors), was etched down to 1 μm contact area with a focused ion beam microscope (FEI DB235).
The mean pore wall width decreased from around 190 nm for the only electrochemically etched samples down to around 80 nm after 48 h of cathodic post-etching.
After development the holes were etched down 30 nm by wet chemical etching (WCE) using H2SO4:H2O2:H2O with a low etch rate of 1 nm/s.
One side of the silicon can then be etched down to within a fraction of a hair's width of the glass layer, leaving the other side as a support.
Using the photoresist as a mask, ILD was etched down to the gate, source and drain regions by RIE.
The etch depth was down to the substrate.
Previous observations have shown that the etch rate slows down by 2% to 3%/μm, and porosity gradients of around 5%/μm occur during anodization of lightly doped silicon [15].
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