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The set of programming voltage during the holding operation will be discussed in the next section.
This decreased tunneling distance causes the BTBT near the drain side during the holding "0", which promotes the accumulation of holes in the potential well during the holding "0", as shown in Fig. 5d.
Usually, the zero bias is used during the holding operation in order to reduce the power consumption [22].
So the more negative Gate2 voltage (−0.5 V) during the holding "0" will degrade the state "0".
With the more negative Gate2 voltage (−0.5 V) during the holding operation, the recombination of holes is eliminated after holding "1", as shown in Fig. 5a, b.
The more holes are accumulated during the holding "0" for S/S/S, so the dropping energy band makes the recombination rate of S/S/S larger than that of S/H/S during reading "0", as shown in Fig. 9.
Similar(22)
a The transient current of DGTFET DRAM cell during the writing, holding and reading operations.
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Creep calculations highlight the time-dependent phenomena occurring during the hold interlude.
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