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Dual-kS JAM device is designed and analysed using source side dual-k and drain side low-k spacers.
For n-channel DWFG EDMOS device fabrication, the polycrystalline-silicon (poly-Si) gate on the source and drain side were doped by p+ and n+ ion implantation, respectively.
The paper presents a comparative study between symmetric and asymmetric straggle architecture, where asymmetric nature is observed by considering straggle in source and drain side alternatively by using the data obtained from 2D numerical simulator Sentaurus TCAD.
This observation has important implications for the scalability of the high-κ dielectric based MOSFET targeted for multi-bit memory application using separate source and drain side hot-electron injection.
Considering the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out using high low (H L), low high (L H) and low high low (L H L) doping profiles for both source (DGS) and drain side (DGD) gate misalignment.
Also, the proposed structure has an extra oxide adjacent to the gate sidewall at drain side.
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The spacers at the source and drain sides have the main influences on performance of DGTFET DRAM.
The HG TFET is composed of different gate dielectric materials at the source and drain sides.
In Fig. 1a, the S_Spacer and D_Spacer refer to the spacers at the source and drain sides, respectively.
In DGTFET, the spacers at the source and drain sides are closed to tunneling junctions, so they greatly affect the performance of DGTFET DRAM.
Therefore, the optimum spacer configuration of DGTFET DRAM is that low-k and high-k dielectrics should be used at the source and drain sides.
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