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In this paper, we design a hardware that can efficiently implement PMI+, which is a Multivariate Quadratic (MQ) asymmetric cipher, for low-resource devices in mobile cloud computing.
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Finally, the emulator was used to design a hardware-in-the-loop test system to analyze the oxygen starvation effect generated by a DC/DC power converter.
Using this model we designed a hardware accelerator for an image reconstruction algorithm for biomedical application.
And then, we designed a hardware configuration of Robot with the abilities to recognize the pose of Target, to measure the distance to Target, and to warn Target in addition to a basic ability to move Robot, based on the model of Robot shown in Fig. 5.
We started with the simplest design from a hardware perspective, building a web server".
The authors presented the design of a hardware called traffic merge network, which merges traffic from multiple links prior to feeding the merged traffic to the switch.
A dual-SIM feature allows it to switch easily between general consumer and government-specific networks, and it features a modular design via a hardware expansion port.
In this work, the design of a hardware component to accelerate reasoning operations on semantic trees by means of an FPGA based platform is presented.
This paper examines and describes the processes of designing a hardware-based rendering engine for a multiple-colour LED display board.
We designed a hardware-in-the-loop (HIL) test bed that provides this information by adapting the tested shunt's environment according to a real-time simulation of the patient.
ASIC design methodology using a hardware design language is dependent on digital simulation.
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