Consequently, some sort of defect and fault tolerance schemes will have to be built into nanoscale circuits, systems, and architectures.
Nanotechnology is yet to come, but even now, in early stage of development it is clear that defect and fault levels will be much higher than current CMOS technology.
He has been general chair of the second MEDIAN Workshop, Program chair of the IEEE Symposium on Defect and Fault Tolerance in VLSI systems, in 2014 and he is General chair of the IEEE Symposium on Defect and Fault Tolerance in VLSI systems in 2015.
Topics include nanoelectronic devices (e.g., graphene and carbon nanotube transistors, quantum dots, etc)., computational paradigms (conventional von Neumann, quantum cellular automata, quantum computing, etc)., microarchitecture and instruction set design specific to nanoscale systems, defect and fault tolerance, fabrication techniques (e.g., self-assembly), modeling and simulation methods.
Interactions between point defects and stacking faults in 3C-SiC are studied using an ab initio method based on density functional theory.
The ordering is reasonably good although point defects and stacking faults are observed in some areas, which may be produced by a variation in sphere size or process fluctuation.
However, these colloidal PBG structures generally have intrinsic defects (e.g., vacancies and faults), leading to relatively low and nonuniform optical performance of the reflective filters.
