Sentence examples for decoder area from inspiring English sources

Significant part of the decoder area is occupied by Configurable Interconnection Network.

An efficient scheme for reducing the memory block number is proposed to increase the memory usage efficiency, so that the quantity of memory bits, decoder area and power consumption is significantly reduced.

Comparison of synthesis results for the network obtained by synthesis of behavioral description as well as the Banyan structural description shows significant decrease of decoder area in the second case.

To evaluate the efficiency of initialization methods, a comparison of their subblock parallelism speedups is accurate enough since the ratios between the BCJR-SISO decoder area and the overall architecture area are very close for both methods (the initialization methods only require memorization overheads, that are negligible with respect to the BCJR-SISO decoder area).

AA-LDPC codes reduce the decoder area and power consumption and improve the scalability of its architecture and so allow the full exploitation of the complexity/throughput design trade-offs.

Behavioral description of the interconnection network gives quite poor synthesis results: decoder area is large and exponentially dependent on the number of inputs / outputs.

The resulting BCJR-SISO decoder requires smaller area (typically 30% less in comparison with others butterfly schemes), but the iterative process has a slower convergence (see Section 4).

For error concealment, the position of the lost areas are identified by the decoder and the damaged areas are substituted by the recovered watermark after an inverse halftoning process.

It achieves additional 0.4 dB coding gain over 14tap parallel decision feedback decoder (PDFD) with 39% area reduction.

Its straightforward "XOR" encoder and one-step majority-voting decoder provide much lower area and higher speed compared with conventional ECCs, and its modular codec structure allows adaptive error correction capability according to the system requirement.

Although supporting higher modulation (i.e., 256-QAM) and larger K i.e., K=21) than the most recent work in [5], the proposed decoder occupies less hardware area.