Sentence examples for d latch from inspiring English sources

It is found that the proposed D latch topology significantly reduces the power consumption and delay in comparison to the traditional PFSCL D latch.

The operation of the proposed D latch is described and is supported with mathematical formulations.

In this paper, an efficient positive feedback source-coupled logic (PFSCL) D latch topology is proposed.

There are several different types of latch, the most common being the D Latch and the SR Latch.

The impact of process variation on the proposed and traditional PFSCL D latch at different design corners shows similar variations.

It uses triple-tail cell concept which results in lesser number of stages as well as gate count in comparison to the traditional PFSCL D latch.

RAM cell designs based on RS-latch and D-latch are investigated with the aim of reducing the area, switching delay, and energy consumption.

In this paper, the low-voltage CML D-latch topology is analyzed and compared to the traditional implementation to evaluate its speed potential and power efficiency, which are crucial aspects in current applications.

The delay expressions derived are used to design and compare the low-voltage and the traditional D-latch both in terms of delay and power-delay tradeoff, by considering a high-performance and a low-power consumption design target.

The proposed design of the divider circuit shows that it is composed of reversible fault tolerant multiplexers, parallel-in parallel out (parallel-in parallelisters, D-Latch, routding and normalization registers and PIPOleft adder.

On the way to design the proposed reversible Plessey Logic Block, each individual components such as reversible D-Latch, reversible Decoder, reversible Multiplexer, reversible Master-Slave Flip-Flop, reversible RAM are designed separately.