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Design procedure incorporates sensor cost, fault detectability and fault detection rate in the design formulation.
The design procedure takes into account three relevant aspects: monetary cost, fault cost (reliability) and robustness (ability to deal with different scenarios of load growth).
Two level networks have been previously proposed that use hypercube and its variants as building blocks; it has been shown that these two level networks are superior to the networks, that are used as building blocks, in terms of various performance metrics including diameter, cost, fault tolerance, fault diameter etc.
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This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors.
This paper presents a very low cost fault-tolerant routing method to tolerate faulty links and routers in mesh-based Networks-on-Chip.
Analytical results demonstrate that the Pars network outperforms known regular networks, namely ABN, ASEN, EGN, and IEGN in terms of cost, fault-tolerance, terminal reliability, mean time to failure, and permutation capability.
Under these conditions, low-cost fault location has become feasible.
Further on, by using the proposed full adder and new arrangements of other reversible gates, some new low-cost fault-tolerant adders including binary coded decimal, carry skip and carry look-ahead architectures are presented.
Thus, for on-board applications, the low-cost fault-tolerant designing is in demand.
These days, when tech departments are pinching pennies harder than ever, Marathon's low-cost "fault-tolerant" system looks better than ever.
In these days, when tech departments are pinching pennies harder than ever, Marathon's low-cost "fault-tolerant" system looks better than ever.
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