More importantly, the projection model is flexible as it can be applied by establishing a CPI measured baseline for a given processor architecture and project from that CPI baseline to a different core frequency of the same processor architecture.
The core frequency of ripple epochs was calculated with three different methods.
Namely, as illustrated in Figure 3C,D, the core frequency of the ripples when Bistrat cells discharged was significantly higher than the core frequency of those ripples during which the Bistrat cells did not discharge (mean core frequency of ripple events without Bistrat cell spikes: 122.5 ± 18 Hz, n = 191 events; with spikes: 140 ± 17 Hz, 347 events; n = 8 cells, p < 0.0001, Mann Whitney test).
Core frequencies of events with or without spikes were statistically compared with Wilcoxon signed rank test.
However, the traditional method of raising core frequency to gain more speed--and thus computational throughput--has recently become limited due to high thermal dissipation, and the fact that semiconductor manufacturers are attacking atomic barriers in transistor design.
However, we would appreciate the authors addressing the following two issues: 1) To support the lumping of the fast frequencies, please show a plot of the distribution of core frequencies for fast frequency events (> 90 Hz) to show that it is not a bimodal distribution composed of distinct fast gamma and ripple events (e.g. as reported by Sullivan et. al).
[Editors' note: further revisions were requested prior to acceptance, as described below.] 1) To support the lumping of the fast frequencies, please show a plot of the distribution of core frequencies for fast frequency events (> 90 Hz) to show that it is not a bimodal distribution composed of distinct fast gamma and ripple events (e.g. as reported by Sullivan et. al ).
In this section, we characterize the Hadoop framework based benchmarks performance and power on ATOM and Xeon-based systems: ATOM D510: · Core Frequency = 1.66 GHz, # of cores = 2, Threads/core =2, L2 cache size = 1 M, DDR2-667/800, Memory BW = 6.4 GB/s.
The total execution time is a function of data block size, Cycles per Instructions (CPI), Path Length (PL), core frequency, processor efficiency, and number of cores: T o t a l E x e c u t i o n t i m e = ( D a t a S i z e × C P I × P L × E f f i c i e n c y ) / C o r e F r e q u e n c y / # o f c o r e s (2).
We verified different processor configurations such as different number of sockets, different number of cores, different core frequency, and different input sizes, with Hyper-threading set to off.
The measurements were taken using Intel Xeon processor (2 sockets, 8 cores, Hyper-Threading On, at 2.7GHz core frequency) which gives a total of 32 threads versus AMD Interlagos (2 sockets, 16 cores, at 2.6GHz core frequency) which also gives a total of 32 threads.
