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By contrast with conventional implementation that requires additional analog electronics, our design is implemented at an FPGA in parallel with many other control and signal processing algorithms.
(a) Conventional implementation and (b) parallel uniform DFT bank implementation.
In the case of the conventional implementation, all inverses in Equation 17 and Equation 13 were replaced with pseudoinverses.
Due to convergence issues with a conventional implementation, we propose a matheuristic based on Benders decomposition for solving the problem.
This enhances the raw needed time for the FFT by 27%% (excluding memory stall gains) over the conventional implementation with twiddle factors.
Compared with the conventional implementation of the correlation in the spatial domain, the benefit of the spectral approach depends on the window sizes.
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Synthesis results prove that the implemented neural network is more compact in terms of size than conventional implementations of a Canny edge detector.
The approach is enhanced over conventional implementations in following aspects.
Substantial gains in computational speed of 20-40% over conventional implementations of the MC technique are obtained over a wide range of densities in homogeneous bulk phases.
It reduces the overall occupied area by 56% and delay time by 6% compared to the conventional implementations which have duplicated operational units.
This algorithm is implemented on an application-specific hardware architecture in an FPGA, which has advantages in throughput and resource usage compared with conventional implementations.
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