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Each PE is configured through a configuration memory, which is organized as a circular buffer.
Moreover, each ASIP is configured through a configuration memory ⑤ which contains all parameters required to perform the initialization of the ASIP.
The fault injection is composed of injecting SEUs into user design memory, and used configuration memory of the exploited FPGA.
In addition, a hierarchical reconfiguration system is used to support a large number of different processing tasks without the power consumption penalty of a big local configuration memory.
Faults are mostly (SEUs) in the configuration memory of SRAM-based (FPGA) and they can change the functionality of an implemented design.
The analytical results reveal that the configuration memory is more significant than design memory to the SEUs due to the relative number of SRAM bits.
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The article designs an overall structure of the shift-register-based configuration memories of the embryonic system and connects them into a chain structure.
Then, the contents of the different configuration memories of the reconfigurable UDec architecture can be generated.
All the material added to support OS in the reconfigurable logic core, concern the configuration memories.
Thus, at run-time, all these parameters need to be computed and loaded into the configuration memories when a new configuration is required.
The different configuration memories are filled through a configuration infrastructure shown in Fig. 4. In order to compute the configuration transfer latency using (11), it is necessary to fix the frequency of the configuration infrastructure.
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