Sentence examples for computational architecture based from inspiring English sources

This manuscript describes the implementation of a general purpose multi-tonal disturbance compensator for active noise and vibration control problems on a high-speed computational architecture, based on a field programmable gate array (FPGA).

This task is approached via Hardware Software (HW/SW) codesign oriented at the Field Programmable Gate Array (FPGA) digital implementation that unifies the NN-adapted image enhancement/reconstruction techniques with a novel efficient computational architecture based on a Network of Systolic Arrays (NSA).

Hybrid computational architectures based on the joint power of Central Processing Units (CPUs) and Graphic Processing Units (GPUs) are becoming popular and powerful hardware tools for a wide range of simulations in biology, chemistry, engineering, physics, etc.

Nandakumar, S. et al. Mixed-precision architecture based on computational memory for training deep neural networks.

To provide an accurate prediction of the displacement and stress fields in an efficient computational framework, a multi-theory architecture based on the Generalized Unified Formulation (GUF) is proposed.

This paper describes a multi-agent architecture based on the actors computational model, for the distributed simulation of discrete event systems whose entities have a complex dynamic behaviour.

The computational complexity of the proposed architecture is about 80% less in comparison with that of the architecture based on number projections in the mixed radix number system.

The proposed prediction architecture is compared to the extended architecture based on 3D-DMB and hierarchical B-picture prediction architectures in terms of computational complexity, memory consumption and coding efficiency.

Experimental results suggest that the proposed architecture exhibits significant computational frame rate performance gains of up to 762.95% in comparison with the conventional centralized video combiner architecture based on a series of four and eight high definition combined video assessments.

It requires less bitrate by on average from 28.7 to 35.4 Kbps, less computational complexity (by on average from 33 to 64%) compared to a codec which deploys the extended architecture based on 3D-DMB or HBP prediction architectures.

This paper describes an architecture based on clusters of embedded "workhorse" processors which can be dynamically harnessed in real time to support a wide range of computational tasks.