TPN Designer consists of two integrated environments: TPN CAD for graphically designing a TPN model and TPN ENGINE for model compilation, debugging, simulation and statistical data collection.
In this paper an approach for automatic variant compilation and simulation model generation, based on mechatronic modules, is introduced.
Verilog hardware description language (HDL) in the Altera's MAX-PLUS II environment has been used for its design, compilation and simulation.
The design, compilation and simulation of the FPGA sub-system were carried out in the Active-HDL environment using the hardware description language VHDL.
The Quartus suite includes compilation, synthesis, simulation, and programming environments.
On the other hand, contemporary ADLs based on their objective can be classified into four categories, which include compilation-oriented, simulation-oriented, synthesis-oriented, and validation-oriented ADLs.
The generated models enable various design automation tasks, including exploration, simulation, compilation, synthesis, test generation, and validation.
The tool suite, named IP Designer, offers fast architectural exploration, hardware synthesis, software compilation, instruction-set simulation, and verification.
The ADL specification is used to generate various executable models such as simulator, compiler, and hardware implementation, and these models can enable various design automation tasks such as exploration, simulation, compilation, synthesis, test generation, and validation.
Quartz is currently the language of the Averest framework (http://www.averest.org), which contains tools for simulation, compilation, verification, and synthesis for Quartz [4].
