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The relaxation map and the compensation diagram were drawn.
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The compensation phase diagram of UPQC-SRI when voltage sag occurs is shown in Fig. 2.
Open image in new window Fig. 4 Negative sequence compensation vector diagram of three-phase MSVC compensation network.
In the resonance state, the working frequency can be given by f = 1 2 π LC (7) Figure 8 Reactive power compensation vector diagram.
Fig. 4 Schematic diagram of compensation light.
In order to validate resistance compensation, resistance compensation block diagram is shown in Fig. 25.
Open image in new window Fig. 2 Principle diagram of the compensation mechanism.
When the shunt current reaches its limit, the phase diagram of voltage compensation is shown in Fig. 7.
This completes the discussion on the proposed CFO estimation and compensation techniques, and the block diagram of the proposed algorithms is shown in Figure2.
ΔU is set as voltage sag depth, so ΔU = (U L -U S )/U L. Fig. 2 Phasor diagram for three basic compensation Strategies.
The block diagrams of the comprehensive compensation strategy for DVR are shown in Fig. 5 in detail.
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