Sentence examples for comparator design from inspiring English sources
In contrast to a recently published randomized controlled parallel group study, in which imepitoin was compared with phenobarbital [ 21], the present study used a low-dose comparator design.
This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure.
In the present work, a double precision floating point comparator design is proposed for efficient floating point comparison.
In this paper, we proposed a novel comparator design based on double tail architecture for an 8-bit successive approximation register analog-to-digital converter.
A low-dose active comparator design was therefore developed to enable demonstration of clinical efficacy of a new drug using a superiority design [ 25].
Data on the RaCTs extracted from the EPARs included therapeutic indication, objective, comparator, design, clinical endpoints, results and the conclusion of the Committee for Medicinal Products for Human Use CHMPP) on comparative efficacy.
The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature.
Moreover, the register file and the tag comparator designed with the proposed circuits respectively show 2.48 and 3 times improvement in the defined figure of merit compared to the counterpart circuits designed with the conventional domino circuit.
Consequently, these aspects may generalize fairly well to other self-controlled designs, but should not be expected to hold for active comparator designs.
As an example, active comparator designs would not be as sensitive as the self-controlled designs to protopathic biases and contraindications, to the extent that these are shared between a drug and an active comparator matched on indication for treatment.
Simulation of register files and tag comparators designed is done using low-Vth 90 nm CMOS process technology model in all process corners.
